Shift register circuits



May 17, 1960 F. c. WILLIAMS ETAL 2,937,288

s HIFT .REGISTER cIRcuITs Filed May 1o, 1954 Attorneys United Sefesifim P 2,937,288 v. y SHIFT REGISTER'cincurrs Frederic Calland Williams and GeorgeT Brianv Barrie Chaplin, Romiley, England, assignors to National Research Development Corporation, London, England, a corporation of Great Britain` j Application May 10, 1954, Serial No. 428,605

Claims priority, application Great Britain May 15, 1,953 Claims. (Cl. 307-885) This invention relates to electrical circuits employing transistors.

vThe specification of copending patent application Serial No. 367,842, tiled July 14, 1953by'fFrederic C; Williams et al., describes a mode of employingtransistors inlelectrical circuits in which the transistor can be triggered from its non-conducting or ofi` condition to a stable conducting or on condition such that the transistor bottoms.

The present invention'relates to circuits for performing the functions of a shift register, employing transistors in the above described regime.

A shift register in the present context is an electronic circuit comprising a series of stages each, adapted to register (for example, by means of an output voltage or current which can occupy one value or another) a digit Velement of one kind or another, the circuit being adapted on actuation by a controlling signal to cause each stage of the series to-impose upon the next succeedingstage the condition it itself registered prior to the controlling signal. Shift registers of this kind are referred to herein as of theV kind set forth. Such circuits are employed for example, in electronic digital computing apparatus operating on the binary system of notation in which digits are represented as either a 0 or a 'l," the different positions of increasing significance representing the ascending h 2,937,288 ,Pia'tentedMay-fl?, 1 960 ICC 2- tionally on the presence for absence of a controlling signal from said memory circuit. l Y t i I According'to the invention in ,another aspecta shift register ofthe kind set forth is provided wherein each stage comprises a transistorr and there are provided means vfor feeding control signalsto the base Aelectrodes of the transistors operating to switch them oif and to condition them to be switched on, means for feeding shift4 signals to the emitter electrodes ofthe transstorsin the appropriate sense and at the appropriate times in relation to's'aid control signals to switch them on, and a memory circuit connected to the collector electrodek of one stage and yto the emitterelectrode of the next succeeding stage adapted to control, lin accordance with the nature of the digit information previously registered by said one stage, whether or not the` transistor of the succeeding stage is switched on by said shift signal. v

According to another aspect ofthe invention a shift register `of the kind v`set forth is provided wherein each stage comprises a transistor and thereare provided means for feeding to the base electrodes of the transistorspulse signals :operating to condition said transistors to'be i the transistor of the succeeding stage effective to procure powers of 2. Obviouslysuch numbers can berepresented by reference to the various states o f a series of two-state circuits, one state of which represents "0 and the other state ofwhich represents 1. It follows that if a series of such twostate circuits has been set up into the various conditions required to represent the ls and Os of `a binary number, this number can, in effect, be multiplied by two simply by shifting all the digitsby one place in the direction of greater significance. Alternatively, division by two corresponds to shifting of the digits by one place in the direction of less significance. Such a process is-frequently required in computing apparatus for the purpose inter alia of multiplication.

In co-pending patent application Serial No. 367,842, above referred to various circuits are described which enable transistors to be used in two-state circuits and basically the present invention employs two-state transistor circuits of this kind vas the individual stages of a shift register.' f

According to the present invention Vin r011e aspect, therefore, afshift register of the kind set forth is provided wherein each stage comprises a transistor and there are provided means for applying signals' from the collector electrode of the transistor of one stage lto a memory circuit and from said memory circuit to the emitter electrode of the transistor of the next stage, applying control signals to the base electrodes of the transistors of each stage to switch them otf, and condition them to be switched on, and means for applying shiftsignals tothe emitter electrodes of the transistors of each stageA at Va time when the transistors are conditioned to be switched on by said control signal to switch the transistors on or not, condiswitchingon Aof said'transistor conditionally on thetransistor of 4the 'onerstage having been switched onr during the previous shift interval. l I f According to a still further aspect of the invention a shiftregister ofthekind set forth is. providedwherein each `stage comprises a transistor andfthere are provided means for feeding tothe base electrodes of the transistors pulse signals operating toswitch said transistors oif during ashortinterval 'of time, means for feeding tofthe emitter electrodes of 'said transistors shift Ysignals immediately following said short intervals; of time and means connected between the 'collector electrode of the transistor of aiirst stage andthe emitter electrode of the v transistor of the suc :ceeding' stage adapted to` provide a signal for the vemitterelectrode ofthe succeeding stage to cause the transistor of 4said ysucceedingstage to be switched on by said`7shift signal conditionally .ont the transistor of said firstl stage having been switched on immediately prior to said'shift interval. `v t VInorder that the invention may be more clearly understood,' an embodiment thereof will now be described with reference to the` accompanying drawings vin which:

'l Figui-el is acircuit diagram showing part of a shift register according to the invention; l

'Figure 2 is a series of waveforms illustrating the operation of the circuit according to Figure 1; Figure 3 is a waveformdiagram illustrating an alternativetmode of operation for Vthe Vcircuit of Figure 1.

YReferring to Figure l, this drawing shows twostages ofa shift register accordingfto the invention, which may consist` of raconsiderable number of. such stages of which the two shown may be anywhere in the series. Each-'of thetwo stages Vshown comprises a transistor T1 and T2 respectively, whichV has `been drawn according to the invention described ined-pending patent application Serial No.,367,842labove-referred to and is fed with defined currents in accordance with the technique of invention disclosed in Athat case. t The potentials applied ktothe various electrodes Yof thetransistorsare alsoA governed, according to the technique of the prior application above referred to, by diodes (which may of course be crystal diodes) and these diodeshave been numbered witha first suix which is related to the location of the diode in the circuit and a second suix indicating the stage in which it occurs. Where in the ensuing description the second sux is omitted, it can be assumed that the point under discussion is applicable to all stages generally. In the circuit of transistor T1, the base electrode is connected to a 50 volt positive supply through resistor R1/1 which is chosen to provide a defined current'of 2 milliarnps to the base electrode.Y The voltage on the base-electrode is restricted in the lpositive sense by diode D5/1 through which it is connected to a' supply at +2 volts and negativegoing so'called clock pulses are applied to the base electrode through a diode D4/ 1. The emitter electrode is tied to volts through a diode D3/ 1 and receives a signal from the previous stage through diodes vD1/1 and D2/1. `An input or shift signal is applied to the junc- Y tion of the diodes D1/1 and D2/1 from an input terminal I through a condenser C1/1 and a resistor RZ/ 1-.

The collector electrode of T1 is connected to 50 volts through a resistor R3/ 1, whereby a defined current of, say, 5 ma. is drawn from it, and its voltage excursion is limited between 0 volts and -10 volts by diodes D7/ 1 and D6/ 1 connected to earth and -10 volts respectively. In addition, the collector electrode is connected to the emitter electrode of the transistor T2 of the next stage through diodes D1/2 and DZ/Z. The junction between the diodes D1/ 2 and D2/2 is also connected to the input terminal I vthrough a resistor R2/2, R3/ 2 and condenser C1/2. This junction point has been labelled A and will be referred to as point A in the following description of the operation of the circuit. The connections to transistor T2 are identical to those of T1.

In the absence of a clock pulse on diode D4 the base electrode of the transistor will `be held at +2 volts by diode D5. The emitter is at 0 volts, being held by diode D3. The transistor is then olf and a voltage of more than +2 v; on the emitter is'required to switch it on.

The circuit according to this invention is primarily of interest in connection with electronic digital computers in which the various processes of the machine are controlled throughout by repetitive pulses, known as clock pulses. The present circuit has these pulses appliedfin negativegoing sense to the base electrodes of all the transistors.`

They are, in the present example, pulses of about 4 volts amplitude between +2 volts .and-2 volts and .5 n sec. duration separated by interval of 1 sec. During the occurrence of these pulses the transistors are all conditioned to be switched on dependently on the voltages at their emitters.

As explained above, the object of a shift register of the kind to which this invention relates is to pass on from each stage to the next the condition previously assumed by the earlier stage and indicative of a given piece of information such as the presence of a l or a 0 in a binary number sequence.V This shift is brought about in the present circuit byV means of shift pulses applied through condenser C1 and resistor R2 to point A. These shift pulses are of about 4 volts amplitude and .25 u sec. duration andare timed to coincide, leading edge `to leading edge with the clock pulses. .Y

Now the potential at point A is controlled by the potential at the collector electrode of transistor T1, which will depend upon whether or notT1 is switched on. On the occurrence ofa shift pulse, therefore, either of two things can occur in the second stage (transistor T2) as follows: Y

v(1') If transistor T1 was switchedvon by the previous shift pulse the condenser C1/2 Will have been charged through D1/2 and point A will ybenear vearthY potential and will be carried-positive by Vthe shift pulse; transistor T2 will thus be switched on, `or v Y (2) If transistor T1 was not switched on by the previous pulsev point A will beat +4 volts and will be .carried only to earth potential by the shift pulse; transistor T2 will not 'be switched on.

The waveform diagram of Fig. 2 will serve to explain the operation of the circuit more fully. In these diagrams it is assumed that a l is indicated by a pulse from a transistor and a 0 by absence of such pulse, and that a l followed by a 0is to be passed on from transistor T1 to transistor T2.- Fig. 2(a) shows the clock pulse waveform and Fig. 2(b) the shift pulse waveform. Fig. 2(c) shows the waveform at the collector electrode of T1 and Fig. 2(d) the waveform at point A, while Fig. 2(e) shows the waveform at the collector electrode of T2.

At tirne to the clock pulse and shift pulse are presumed to switch on T1 by virtue of the potential existing at the junction of vD1/1 and D2/1 due to the previous cycle. The collector. electrode .of T1 thus rises' from its resting potential of -lOvolts towards earth thus charging condenser Cl/Z through R2/2 and raising the potential o point A. i Y The collectorgcurrent must rise to its full amplitude lbefore the shift'pulse ends at time t1. The clock pulse switches off T1 at time t2. o

Meanwhile, in transistor T2 the clock pulse has prepared T2 to be switched on, but point A having been at +4 volts (as will be apparent later) the shift pulse raises the emitter electrode of T2 only to earth potential (or thereabouts) so that T2 is not switched on." i v yThus T1 has registered a l and T2 a. 0, butlpoint A has now been raised to about --.1.5 volts.

0n arrival of the next vclock and shift pulses `(time Yt3) T2 will be switched on as was T1 in the` previouscycle, since the shift pulse will tend to raise point A from 41.5 volts to 2.5 volts. However, diode D7/2 prevents the collector elect-rode of T2 from rising above zero potential and hence the emitter aboveabout +l.5 volts. Current thus flows from C1/ 2 into the emitter of T2 through DZ/Z. At time t4, the end of the shift pulse, point A will ybe at .about zero potential and lwill therefore be brought down, by cessation of the shift pulse'to -4 volts. .At ktime t5 the end ofthe clock pulse switches olf: T2. T2has thus .delivered a S/i sec. pulse indicating a 1.

Meanwhile, on occurrence of this second shift pulse, the junction between Dl/l and D2/ 1 was at -4volts, ja 0 having followed the l and'transistorhT1 was not therefore switched on. Point A (andthe junction of D1/1 and D2/ 1) lwill continue to be switched between -4 volts and zero by each shift pulse and the 'transistors will not be switchedon until such time Yas a further 11l causes T1 to be switched on as first described.

The time that can elapse between the transistors switching off and the arrivaly of the next input pulse will depend on the time taken for C to lose appreciable charge through the back resistance of diodes D1 and D2, thus for low pulse repetition frequencies the on states should be made l correspondingly longer to prevent the memory con? tained in condenser C from being lost during the time all transistors are olf. f

The function of D7/2 is to allow rapid discharge of C when a "1 appears at T2. It may be replacedfhowever, by a. condenser and resistance in series from T2 collector to earth of value similar to C and R. If this is donethe clock waveform may be dispensed with and the onr state made self terminating by replacingD4 by a suitable inductancefrorn base to +2 v. and reducing the .collector current from 5 ma. to 3 ma.

The circuit Vmay also be made to operate non-repetitive ly, i.e. with long, possibly variable, times between vsuccessive shifts. To do this it is necessary to maintain the transistors normally `switched on to indicate a "1 (or off to indicate a 0), during thetimes between shifts. The operation of the circuit is then as follows:

Referring to the waveforms of Fig. 3, Fig. 3(1) shows a clock pulse which is in this case positive-going and which will be gated so as to be applied tothe transistor base electrodes only when a shift is to be eifezted.v YThe i corresponding shift pulse is shown' at Fig. 3(b) and will be seen to occur immediately after the clock pulse.

The effect then is that, on arrival of a clock pulse all the transistors which were on are switched off for the duration of the clock pulse, at the end of which the base electrodes will all be restored to -2 volts to condition the transistors to be switched on again. On occurrence of the immediately following shift pulse those transistors will be switched on which experience a suitable voltage at the diode junction D1, D2 (Point A). These will, o-f course, be those in the stages following the transistors which were previously switched on, this fact being remem bered by the corresponding condenser C1 so that a shift of one place is achieved.

It will be apparent that the circuit according to the invention can be set up to register a given sequence of ls and Os by feeding in the appropriate digit signals serially at one end or alternatively by feeding in suitable signals -in parallel to the diode junctions D1, D2.

We claim:

1. A shift register circuit comprising a plurality of stages each of which comprises a transistor, a memory circuit, and means for applying a first control signal having one of two possible values from the collector electrode of said transistor of one stage to said memory circuit, and from said memory circuit to the emitter electrode of the transistor of the next stage, means for limiting the upper value of said first control signal, means for applying second control signals to the base electrodes of the transistors of each stage to switch them olf and condition them to be switched on, and means for applying simultaneously with the application of said second control signals to said base electrodes shift signals to said memory circuit to augment said rst control signals to switch the transistors on or not, conditionally on the value of said irst control signals.

2. A circuit according to claim 1 wherein said memory circuit comprises a condenser adapted to be charged under the control of said limiting means from the collector eleotrode circuit of said one stage when the transistor of that stage is switched on and wherein said shift signals are applied to the emitter of the succeeding stage through said condenser whereby the voltage to which said emitter is taken by said shift signals is dependent upon the state of charge of said condenser.

3. A circuit according to claim 2 wherein the collector electrode of said one stage is connected to a diode poled to conduct when the voltage on said collector electrode rises to a predetermined value due to switching on of the transistor of that stage, thereby to limit the charging of said condenser.

4. A circuit according to claim 3 wherein said condenser is connected through a resistor to said collector electrode through a diode poled in the appropriate sense to conduct when the voltage on said collector electrode rises due to switching on of the transistor, and to said emitter electrode through said resistor and a further diode poled to transfer positive-going signals from said condenser to said emitter.

5. A shift register circuit comprising a plurality of stages each of which comprises a transistor, a connection of the collector electrode of said transistor of a first stage through a diode to one side of a condenser and from the same side of said condenser through a further diode to the emitter electrode of the next following stage, a connection of said collector electrode through an impedance which is high compared with the internal impedance of said first transistor in its conducting state to a negative supply potential, diodes connecting said collector electrode to each of two bias potentials whereby the voltage excursions of said collector are limited between a lixed negative bias when said iirst stage transistor is non-conducting and an upper bias when said first stage transistor is conducting, a source of control signals connected to the base electrodes of all of said transistors adapted to switch said transistors olf and condition them to be switched on, and a source of shift signals connected to the other side of said condenser and adapted to augment a signal stored on said condenser to raise the potential of the emitter electrode of said next following stage transistor at a time when said transistors are conditioned by one of said control signals to be switched on so as to switch said next following stage transistor on or not conditionally on the value of the signal stored on said condenser.

References Cited in the le of this patent UNITED STATES PATENTS 2,580,771 Harper Ian. 1, 1952 2,591,961 Moore et al. Apr. 8, 1952 2,760,087 Felker Aug. 21, 1956 2,847,159 Curtis Aug. 12, 1958 

